Correlator

Firmware Change Log

Version 1.3.0

First working version, cross correlation of 2 inputs, 32 lags, UDP over Ethernet data transport.

Version 1.4.0

Added a configurable (4096-point max) delay line after each input, for a total of 8192 delay steps. The length of each line can be set using the embedded processor on the V2.
Changed the length of the lag accumulation registers from 32 to 48 bits (max available in a single DSP48 block). Each register must be read onto the V2 wishbone bus in two groups of 32 (the values are sign extended into the unused higher order bits).