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Firmware Change Log

Version 1.7.0

  • First operational release.

Version 1.8.0

  • Added the option to under-sample the incoming data before the FFT (to work around the lower input clock limit of 32 MHz specified in the Virtex4 user’s guide).

Version 1.8.4 (incorporating a number of intermediate stages that weren’t independently released)

  • Fixed a number of stability issues with the GUI and survey_dual.
  • Increased the internal precision of the FFT to 10 bits to avoid problems caused by integer scaling.
  • Re-routed the global reset signal to (hopefully) fix poor signal-to-noise ratio.
  • Divided the core into wide- and narrow-band versions to increase the speed of the wide-band core.

Version 1.8.5

  • Disabled the FFT auto-scaling feature and experimented with a wider data path in an attempt to remove high-frequency artifacts.

Version 1.8.6

  • Applied a window function to the input data before it reaches the FFT. Each 6-bit sample is multiplied by a 6-bit number representing a coarse Hann window (stored in ROM on the FPGA). This reduces the spectral leakage caused by discontinuities at the edge of an FFT “frame”, effectively removing all high-frequency artifacts.
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Page last modified on January 15, 2008, at 02:31 AM