Here you will find information about the FPGA-based instrument development project underway within the radio astronomy group at the University of Tasmania. We are currently developing core designs (IP) for our own radio processor board (nicknamed TasPGA).
TasPGA is a flexible instrument; the signal processing capabilities that it provides can be used to perform a number of different experiments or tasks. Currently, FPGA firmware exists for the following applications:
A set of development notes have been compiled to assist newcomers.
TasPGA is a simple, high-speed digital processing board designed for radio astronomy applications. It has 3 FPGAs, a small amount of memory and a lot of high-speed digital I/O lines that can be connected to a sampler or used to daisy-chain several boards.
During a UTas workshop on FPGA technology and its use in radio astronomy in February 2007, a group of participants set up a web-based forum to promote discussion of FPGA design methods. It can be accessed at the following URL:
The first Programmable Logic Array (PLA) devices were introduced in the early 1970′s. These early devices contained arrays of fixed logic components that could be configured to operate on any combination of the available inputs. As technology advanced, other forms of the Simple Programmable Logic Device (SPLD) evolved. Most of these were variations on the original theme, some utilising a mix of configurable and non-configurable pathways to reduce the overall complexity of the device and allow increased input capacity.
In the 1980′s, manufacturers started to combine multiple SPLDs into single elements known as Complex Programmable Logic Devices (CPLDs), further increasing the power and capacity of this technology. Various types of CPLD are commercially available today. A certain amount of user-configurable interconnection (between discrete SPLD elements) is required to make a CPLD work, but CPLDs are based around fixed logical operations and their internal architecture does not scale well to high logic densities or I/O capacities.
The Field Programmable Gate Array (FPGA) arrived on the commercial scene in the mid-1980s, offering a new approach to the concept of programmable logic. An FPGA differs from a CPLD in that it consists of an array of Configurable Logic Blocks (CLBs) that are not committed to any particular operation. The structure of an FPGA is dominated by interconnections between large numbers of CLBs, naturally forming a regular physical lattice that is easy to manufacture. This allows very high logic densities to be achieved within a single chip.
In the past few years, manufacturing processes have been refined to the point where millions of gates can be laid down in a single FPGA. This has led to the concept of “system-on-chip” design, allowing complicated digital circuitry to be replaced by a single slice of silicon. The architecture of FPGAs makes them very flexible and useful for system integration (linking various components). Manufacturers are now offering FPGAs that contain large amounts of specialised hardware within the fabric of the device itself. These additional hardware elements include multipliers, serial I/O transceivers and even whole 32-bit microprocessor cores. Coupled with large amounts of internal memory, a modern FPGA has the capacity to encapsulate a design that would in the past have required a complicated printed circuit board of its own.
Some of the best modern FPGAs can operate at clock frequencies approaching 500 MHz, allowing them to perform real-time signal processing. DSP-optimised FPGAs have advantages over dedicated DSP chips in that they perform complicated tasks almost as quickly and also have the power of configurable logic, which makes system integration much easier and in-system reconfiguration possible.
Radio astronomers have been using FPGAs in their instruments for a decade or more, but the modern generation of commercial devices have capabilities that far exceed anything previously available. Many algorithms that could in the past only be executed on a general purpose processor could be migrated to a large FPGA and optimised for real-time operation. This will be crucial to the feasibility of next generation telescopes (like the SKA) that use massive arrays of antenna elements.